1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device with a voltage select circuit, and more particularly to an erasable programmable read only memory (EPROM).
2. Description of the Related Art
In a conventional semiconductor memory device of the nonvolatile type, such as an EPROM, a high level potential is applied to the selected word line. This potential must be changed in such a way that it is 12.5 V in a write mode, while it is 5 V in a read mode. It is for this reason that a voltage select circuit is used in the memory device.
FIG. 1 shows a circuit arrangement of a conventional memory device made up of metal oxide semiconductor (MOS) transistors. Reference numerals 102, 104 and 106 designate a power voltage select circuit, a row decoder and a memory, respectively.
In a write mode for writing data into memory 106, write potential Vpp, e.g., 12.5 V is applied to nodes 3 and 6 of voltage select circuit 102. Read potential Vcc, e.g., 5 V, lower than Vpp is applied to node 4. Ground potential GND is applied to node 7. Under this condition, depletion type N channel MOS transistor 1 is turned on, while depletion type N channel MOS transistor 2 is turned off for the moderate threshold voltage of depletion type transistor 2.
When, however, the threshold voltage of depletion type transistor 2 is relatively large, a channel is set up between the source and drain of the transistor even if node 7 is placed at ground potential. Therefore, if a potential difference exists between the source and drain, current flows through the source-drain path and the potential at node 5, is pulled toward Vcc potential, resulting in a voltage reduction from Vpp (12.5 V) to a potential equal to Vpp minus the potential shifted toward Vcc.
In a read mode, Vpp potential is applied to node 3. Read potential Vcc is applied to nodes 4 and 7. Ground potential GND is applied to node 6. Under this condition, transistor 1 is turned off, and transistor 2 is turned on. As a result, read potential Vcc appears at node 5. Address signals from a row address buffer (not shown) are applied as an address input to NAND gate 8 of row decoder 104. When address signals are all logical "1", a logical "0" signal is output. In other conditions, a logical "1" signal is output. This signal is input to the gate of depletion type MOS transistor 10 and the input terminal of CMOS inverter 15 made up of enhancement type N channel MOS transistor 11 and enhancement type P channel MOS transistor 12.
In a read mode, read potential Vcc is applied to node 5. If address signals to NAND gate 8 are all logical "1", NAND gate 8 outputs a logical "0" signal. This output signal is applied to the input terminal of CMOS inverter 15. In turn, P channel MOS transistor 12 of inverter 15 is turned on, while N channel MOS transistor 11 is turned off. Read potential Vcc is applied through P channel MOS transistor 12 to word line 14. The result is that word line 14 is selected, a corresponding memory cell in memory 106 is selected, and data is read out from the memory. Actually, to select the memory cell, the bit line associated with the selected memory cell must be selected. This is not essential, and hence no further description of it will be given here.
In a write mode, potential Vppa, equal to Vpp minus the potential shifted toward Vcc, is applied to node 5. When address signals applied to NAND gate 8 are all "1's", this gate 8 outputs a "0" signal. The output signal from NAND gate 8 is input to the input terminal of CMOS inverter 15, so that P channel MOS transistor 12 of inverter 15 is tuned on, while N channel MOS transistor 11 is turned off. Then, potential Vppa is applied via transistor 12 to word line 14. Finally, word line 14 is selected, a corresponding memory cell of memory 106 is specified, and data is written into the memory.
In an EPROM, a high potential is applied to the control gate, so that electrons are generated due to avalanche occurring in the vicinity of the drain. The electrons are absorbed by the control gate for data writing. In this type of the semiconductor memory device, if a write potential is lower than a predetermined potential, electrons are insufficiently absorbed by the control gate, possibly causing an erroneous data write.
In the power voltage select circuit as mentioned above, the potential appearing at node 5 is reduced from the write potential Vpp. Therefore, an insufficient number of electrons are injected to the control gate, possibly causing an erroneous write operation.